1. Field of the Invention
This invention is related to ferroelectric memories, and, more particularly to a bit-line shielding method specifically adapted for ferroelectric memory architectures.
2. Background of the Invention
Capacitive coupling among bit-lines is one of the major noise sources in a semiconductor memory such as a ferroelectric memory. This coupling sometimes is so strong that it causes read fails if no appropriate measure is taken. There are typically two conventional methods to solve this problem. The first method is twisting the bit-lines to reduce coupling. The second method is adding an additional shielding metal line between each pair of bit-lines.
Bit-line twisting has several disadvantages. Bit-line twisting is most effective when the twisted bit-lines carry electrically complementary signals. Thus, the effect of bit-line twisting is data dependent and the coupling is random, increasing the difficulty of the reference design. Coupling among bit-lines can only be balanced by bit-line twisting, but not eliminated. Bit-line twisting complicates layout and increases the imbalance between the bit-line and the electrically complementary bit-line.
The disadvantage of conventional bit-line shielding is that extra lines are added to the memory core; thus the die efficiency is reduced.
What is desired is a compact bit-line shielding technique that is specifically suited to both referenced and self-referenced ferroelectric memories.
A bit-line shielding technique for a ferroelectric memory logically divides the bit-lines in the array into two groups. In a preferred mode of operation, only bit-lines in one of the groups are accessed at a time. When the bit-lines in one of the groups are accessed, the bit-lines in the other group are not accessed and thus can be grounded to electrically shield the bit-lines being accessed. Each group of bit-lines is coupled to the drains of a group of pre-charge devices at the bottom of the array. The sources of the pre-charge devices are grounded. The word lines are arranged so that only the bit-lines in one of the groups are accessed at a time. Thus, when the bit-lines in one group are accessed, those on the other group can be grounded to shield the bit-lines being accessed by controlling the state of the pre-charge devices. One dummy bit-line, which is always grounded, is put on each side of the array segment. In this way, each bit-line can be shielded by two grounded lines on both of its sides when accessed.
The bit-line shielding technique of the present invention can be expanded by logically dividing the bit-lines into three or more sub-groups if desired. The minimum useful grouping includes two bit-lines, so that at least one accessed bit-line can be shielded. During a memory access, some of the groups are accessed and others are not as desired. The bit-lines in the groups which are not accessed are grounded to shield the bit-lines in the groups being accessed.
It is an advantage of the invention that each bit-line is shielded by grounding two unused bit-lines on each side. The coupling among the bit-lines is essentially eliminated without adding extra metal shielding lines so the physical layout of the ferroelectric memory array is simpler than bit-line twisting.